Callled Talus, the new software rather than providing electronic design assistance, offers advanced implementation capabilities in Talus are designed to dramatically reduce the design development cycle and design costs, and speed yield ramp-up for ICs targeted at 65-nanometer (nm) and smaller process geometries.

According to Rajeev Madhavan, CEO of Magma, "At each process node, development costs are increasing and profits per design are decreasing. To reverse that trend, IC vendors need true design automation so they can accelerate the design cycle and maximize their engineering resources - that's what Talus delivers."

Talus provides a complete RTL-to-tape-out platform that concurrently analyses and optimises timing, area, power, signal integrity and yield. It enables 'automated chip creation', a new methodology for IC implementation that drastically improves engineering productivity. It also transforms floor planning into an automated physical synthesis process. Leveraging a new constraint set called 'relative placement constraints'; Talus eliminates the need for the traditionally labour-intensive and time-consuming floor planning and prototyping tasks. Design for variability on complex designs is supported through concurrent multi-mode/multi-corner and native on-chip variation (OCV) analysis with timing and cross talk noise optimisations.

Moreover, its advanced timing capabilities eliminate the need for iterative analysis and optimisation runs to meet multiple mode and corner constraints. Talus also incorporates sophisticated routing algorithms developed in conjunction with IBM and the University of Bonn. Talus is the first system in which the entire implementation flow is lithography-aware. This unique capability minimizes the key source of deterministic variability in 65- and 45-nm designs.

Talus' 'automated chip creation' methodology enables designers to create either preliminary or final-quality layouts, physically flat or hierarchically, in a few hours and for any size design. The process can begin with as little as 10 per cent of the design RTL available.

Users can identify the top-level timing constraints that meet block-timing budgets, enabling them to avoid timing violations later during chip integration. With each subsequent RTL change, Talus automatically creates multiple floor plans, allowing designers to see in real-time the impact of those changes on chip size.

Predictability for subsequent trials is managed with the 'relative placement constraints', which enable the user to reproduce desired aspects of a previous floor plan. This unprecedented level of automation expands the user's efficiency at all stages of design development. Early in the process, fast implementation trials can be conducted to establish accurate timing constraints, investigate floor plan alternatives, and trade off package decisions with respect to design speed, area, noise, yield, and power integrity. Late in the process, the schedule impact of late-arriving RTL and design requirement changes is minimized because the required production floor plan changes are handled automatically.

To further accelerate the design cycle and provide the highest capacity, Talus leverages multithreading and distributed processing, allowing users to implement very large designs in just two days. With faster design cycles, higher capacity and the ability to automatically and effectively address all design objectives, Talus users will be able to devote more time to product innovation, reduce IC development costs and increase yields.

Beta Results Demonstrate High QoR and Overnight Runs
A number of full-chip designs targeted for various applications and ranging in size from 4 to 15 million gates have been taken through the Talus flow. Results have demonstrated productivity improvements and significant area savings over conventional design techniques.

"Hierarchical design demands a significant amount of time and number of resources, especially when the RTL code is changing," said John Fallin, executive director, Custom SOC Engineering, NEC Electronics America, Inc. "By using Talus, we will have a viable flat design methodology for 12-million-gate and larger chips that is able to confirm new floorplans overnight, quickly validate chip-level timing constraints, and give us confidence that the design is production worthy."

The two products Talus LX and Talus PX provide the foundation of the automated chip creation methodology for logic and physical design engineers. Both are built on Magma's unified data model architecture offering a tightly integrated IC implementation flow. Talus LX synthesizes chip RTL for given timing, power and placement constraints and automatically generates physical partitions and power and clock prototypes. This automated solution empowers logic designers to rapidly explore the design space and implement the most optimal solution without detailed knowledge of physical design and without sacrificing the schedule, or quality of the design. Talus PX provides complete physical implementation of the design including near abutment layout, final physical partitions, power and signal routing, and chip-level clock tree synthesis. This integrated physical design environment delivers improved timing and signal integrity, smaller area, lower power, better manufacturability, faster turnaround time and higher capacity than conventional point-tool flows.

Both products are currently in limited release. Pricing will be available with the production release scheduled for 2006.

Magma's software for integrated circuit (IC) design is recognized as embodying the best in semiconductor technology. The world's top chip companies use Magma's EDA software to design and verify complex, high-performance ICs for communications, computing, consumer electronics and networking applications, while at the same time reducing design time and costs. Magma provides software for IC implementation, analysis, physical verification, characterization and programmable logic design, and the company's integrated RTL-to-GDSII design flow offers