Hyderabad: Synopsys Incorporated (Nasdaq: SNPS), has launched Design Compiler(R) FPGA (DC FPGA), a new FPGA synthesis product targeted at designers who prototype ASICs using high-end FPGAs.

Built on Synopsys' Design Compiler technology and incorporating new adaptive optimisation (TM) technology, DC FPGA provides designers with an industry standard ASIC-strength solution, the best circuit timing results, and the fastest path to a prototype, through a common ASIC and FPGA flow. To date, over 40 customers have purchased DC FPGA and 20 prototype designs have been successfully completed.

Today's ASIC designers are faced with a multitude of prototyping challenges. Most ASIC prototypes require the largest, most advanced FPGAs available. These FPGAs are extremely complex and need an ASIC-like methodology. Many of these ASIC prototypes are required to run at full speed, particularly for wireless designs, therefore timing quality-of-results (QoR) is critical.

In addition, using incompatible synthesis solutions involves a time-consuming and error-prone manual effort to move designs between the ASIC and the prototype. Usually, RTL code, synthesis constraints, scripts and the ASIC IP must be changed, making this step as difficult as designing another chip.

In contrast, DC FPGA's compatibility with Design Compiler enables the integration of the ASIC and FPGA design environments. DC FPGA accepts the same RTL code, constraints, scripts, and IP libraries as Design Compiler, and provides the same interface to Formality (R) formal verification. This enables a seamless migration between ASIC and FPGA flows, eliminates manual changes and provides the fastest path to ASIC prototype. Designers prototyping using DC FPGA only need to design once, and benefit from the power of ASIC tools, like Formality, Leda), PrimeTime and the extensive DesignWare libraries for their prototype.

DC FPGA's adaptive optimisation technology contains new, advanced optimizations that automatically activate the best core synthesis algorithms based on multiple parameters, including design size, circuit topology and timing constraints, then dynamically control and reorder how the algorithms are applied. The resulting circuits produced by DC FPGA operate, on average, 15 percent faster than those produced by traditional FPGA synthesis products.